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The conversion rate is programmed by setting the ADC_RATE bits in the ADC_CFG register. The analog input of
the ADC can be chosen from various sources and is configured with the ADC_SEL bits in the ADC_CFG register.
As described in Table 34, the ADC inputs can be single-ended (routed individually to ADC0, ADC1, ADC2, or
ADC3) or differential (routed to pairs ADC0-ADC1 and ADC2-ADC3). For selecting alternate pin functions, refer
to Table 17 and Table 18.
Table 34. ADC Inputs
ADC_SEL[3:0]
0
1
2
3
4
5
6
7
8
9
10
Analog Source of ADC
ADC0
ADC1
ADC2
ADC3
(1/4) * VDD_PADS (2.1–3.6V pad supply)
(1/2) * VDD (1.8V core supply)
RESERVED
VSS (0V)
VREF
ADC0–ADC1
ADC2–ADC3
GPIO Pin
4
5
6
7
8
4–5
6–7
Purpose
Single-ended
Single-ended
Single-ended
Single-ended
Supply monitoring
Supply monitoring
Calibration
Calibration
Differential
Differential
Setting the ADC_EN bit in the ADC_CFG register will cause the ADC to immediately begin conversions. The ADC
will continually generate conversions until the ADC_EN bit is cleared. When each conversion completes, an
INT_ADC interrupt is generated. In order for this to interrupt the CPU the interrupt mask INT_ADC must be
enabled in the INT_CFG register. The INT_ADC interrupt is the only means for determining when a conversion
completes. After each INT_ADC interrupt, the INT_ADC interrupt bit must be cleared to detect completion of
the next conversion.
To ensure the pipelined digital filter in the ADC is flushed, ADC_EN should be cleared before changes are made
to ADC_SEL or ADC_RATE . Discard the first sample after ADC_EN is set.
The ADC uses an internal reference, VREF, which may be routed out to the alternate pin function of GPIO8,
VREF_OUT. VREF_OUT is only enabled when the ADC_EN bit in the ADC_CFG register is set. VREF is trimmed as
close to 1.2V as possible by the EmberZNet PRO software, using the regulated supply (VDD) as reference. VREF
is able to source modest current (see Table 36) and is stable under capacitive loads. The ADC cannot accept
an external VREF input. For selecting alternate pin functions, refer to Table 17 and Table 18.
While the ADC Module supports both single-ended and differential inputs, the ADC input stage is differential.
Single-ended operation is provided by internally connecting one of the differential inputs to VREF/2 while fully
differential operation uses two external signals. The full-scale differential input range spans -VREF to +VREF
and the single-ended input range spans 0 to VREF.
Sampling of internal connections VSS and VREF allow for offset and gain calibration of the ADC in applications
where absolute accuracy is important. Measurement of the unregulated supply VDD_PADS, 2.1-3.6V pad
supply, allows battery voltage to be monitored. Measurement of the regulated supply VDD, 1.8V core supply,
provides an accurate means of calibrating the ADC as the regulator is factory trimmed to 1.72V.
Offset and gain correction using VREF or VDD reduces both ADC gain errors and reference errors but it is
limited by the absolute accuracy of the supply. Correction using VREF is recommended because VREF is
calibrated by the EmberZNet PRO software against VDD, which is factory trimmed to 1.72V. Table 35 shows
the equations used.
120-0082-000V Rev 1.1
Page 98
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